Nvidia's next-gen Groq LPU tipped to adopt 3D stacked DRAM
10/21/2026 — 10/21, 16:16·2 sources (all)·2 reports (all)
Key takeaways
- Citing ZDNET Korea, reports say Nvidia's next-generation Groq LPU inference accelerator may adopt TSV-based 3D stacked DRAM, dropping the la…
- Cerebras, which also leans on large SRAM, has already teased 3D vertically integrated DRAM for CS-6.
Background & analysis
On October 21, 2026, IT之家 reported, citing a story published the previous day by Korean outlet ZDNET Korea, that NVIDIA's next-generation Groq LPU AI inference accelerator chip may move to a 3D stacked DRAM approach built on TSV (through-silicon via) technology, dropping the large-capacity SRAM cache design used in the current generation. The report's stated reasoning is that SRAM offers limited capacity and yields little density gain from process upgrades, which places inherent constraints on performance with large models and on chip iteration.
The same report notes that Cerebras, which also follows a large-SRAM route, had previously said its future CS-6 would vertically integrate DRAM in 3D. That is where the available information currently stands: the report only says the next-generation Groq LPU may adopt 3D stacked DRAM, without giving a timeline, a product version number, or performance figures, and the materials contain no response from NVIDIA.
AI-generated from 1 reports · updated 7 hours ago
Latest turnAccording to cnBeta, AI inference chipmaker Groq plans to adopt 3D stacked DRAM technology instead of SRAM in its next-generation LPU products to address growing capacity demands for large AI models.
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Reports on this story headlines open the original
According to cnBeta, AI inference chipmaker Groq plans to adopt 3D stacked DRAM technology instead of SRAM in its next-generation LPU products to address growing capacity demands for large AI models.
cnBetaAI score 63Citing Korean outlet ZDNET Korea, ITHome reports that NVIDIA's next-generation Groq LPU AI inference accelerator may adopt 3D stacked DRAM built on TSV, dropping the large-SRAM cache design used in the current generation. The report notes that SRAM offers limited capacity and diminishing density gains from process upgrades, constraining large-model performance and chip iteration. Cerebras, which also relies on large SRAM, has already said its CS-6 will vertically integrate DRAM in 3D.
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