Intel CTO says leading-edge wafer output can at most double

On October 23, 2026, IT之家 reported that Intel CTO Pushkar Ranade discussed the limits of leading-edge wafer capacity on the Dwarkesh podcast. Asked whether the world has enough tools to raise leading-edge wafer output tenfold, he replied that the answer is not 10x but perhaps 2x, meaning that even with ample funding, global production of advanced wafers can realistically grow by roughly a factor of two.

Ranade attributed that ceiling to the ability of the entire semiconductor supply chain to expand in step, rather than to any single link. He noted that AI compute has grown roughly threefold per year over the past decade, but the key equipment, cleanrooms and fab scale needed to make advanced chips are becoming the new capacity ceiling. ASML produces fewer than 100 EUV lithography machines a year and is unlikely to expand output substantially before the end of the decade, while Intel, TSMC and memory makers such as SK Hynix compete for those machines.

On timing, Ranade said equipment ordered today typically arrives about 18 months later, so capacity would only come online around 2028. Building a new fab does not automatically yield more wafers, largely because equipment supply cannot keep up. Raising overall output would require equipment suppliers, their own suppliers and lower-tier subcontractors to add capacity simultaneously. The report ends there and does not mention Intel's own capacity plans or related investment arrangements.