Qualcomm validates HBC memory to replace HBM for AI inference

On November 2, 2026, Qualcomm announced that its first-generation High Bandwidth Compute (HBC) technology had completed hardware validation at its San Diego lab, confirming full read and write capability as well as near-memory compute functionality, and delivering 133 TB/s of memory bandwidth. HBC is a near-memory compute architecture Qualcomm developed for AI inference. Rather than following the traditional HBM approach of stacking DRAM dies to raise bandwidth, it stacks multiple layers of LPDDR memory vertically above a compute chip, with the compute die placed at the base of the stack, shortening data paths from the several centimeters of conventional architectures to a few microns. Interconnections between dies are made through through-silicon vias (TSV). Qualcomm says the design uses LPDDR's relatively low power consumption and the tight integration of memory and compute to improve data-movement efficiency in AI inference workloads. The AI250 accelerator built on this architecture is scheduled to sample in the first half of 2027, so no samples have been shipped yet. According to the report, this marks the LPDDR-instead-of-HBM memory approach for inference entering the productization stage.