Huawei Releases Kirin 9050 Series Chip Featuring New DaVinci Architecture NPU

On 11 November 2026, Huawei Kirin officially published a post on its WeChat official account unveiling the Kirin 9050 series, described as its first τ chip built on the company's "logic folding" technology. The series carries a new-generation Da Vinci architecture NPU, which the company claims delivers a 140% performance increase and 66% lower power consumption, along with support for the Transformer engine, an ultra-low-power perception engine, and the CANN heterogeneous computing architecture.

Huawei positions the Kirin 9050 series as the industry's first mobile chip capable of running a 30B MoE large model on-device, supported by multi-level memory-computing collaboration optimization and low-bit quantization. Building on this NPU, the chip powers a set of on-device AI features that work without a network connection or cloud access: AI screen reading that senses the display, Xmage智拍 2.0 that senses images, AI eye-tracking page turning that senses the user's gaze, and an always-on map 2.0 that senses location.

Earlier, at the 2026 Kirin media briefing held in October 2026, Xu Songyu, head of wireless terminal chip product management at Huawei's semiconductor business, said the Kirin 9050 series, as the first logic-folding τ chip, would open a new decade of development. Presentation slides shown at that event stated Huawei aims to push P-core frequency past 5GHz by 2031. So far, public information about the series is limited to this launch material; no follow-up details on supply availability or the devices that will carry the chip have been reported.